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Clock Generators for SOC Processors
Phase-Locked Loop Fundamentals -- Low-Voltage Analog Cmos Design -- Jitter Analysis in Phase-Locked Loops -- Low-Jitter PLL Architectures -- Digital PLL Design -- DSP Clock Generator Architectures -- Design for Testability in PLLs -- Clock Partitioning and Skew Control.Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless tra…
- Edisi
- 1st ed.
- ISBN/ISSN
- 9781402080807
- Deskripsi Fisik
- XVIII, 246 p. 213 illus.online resource.
- Judul Seri
- -
- No. Panggil
- -
Karya Umum 
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Kesenian, Hiburan, dan Olahraga 
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